Although in principle applicable to arbitrary integrated circuits, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.
FIG. 1 shows a schematic cross-section of a semiconductor memory cell having a trench capacitor and a planar selection transistor connected thereto.
In FIG. 1, reference sign 1 denotes a silicon substrate. In the semiconductor substrate 1, trench capacitors GK1, GK2 are provided which include trenches G1, G2, the electrically conductive fillings 20a, 20b thereof forming capacitor electrodes. The conductive fillings 20a, 20b are isolated by a dielectric 30a, 30b with respect to the semiconductor substrate 1 in the lower and medium trench region, said substrate 1 forming the second capacitor electrodes (e.g. in form of a buried plate not shown).
In the medium and upper region of the trenches G1, G2, surrounding isolation collars 10a, 10b are provided, above which buried contacts 15a, 15b are provided which are in electrical contact with said conductive fillings 20a, 20b and the adjoining semiconductor substrate 1. The buried contacts 15a, 15b are connected to the semiconductor substrate on a single side only (cmp. FIG. 2a,b). Isolation regions 16a, 16b isolate the other substrate side with respect to the buried contacts 15a, 15b and isolate the buried contacts 15a, 15b to the top of the trenches G1, G2.
This arrangement allows a very high packing density of the trench capacitors GK1, GK2 and the associated selection transistors which will be explained in the following. In this respect, the selection transistor associated to the trench capacitor GK2 will be mainly referred to, because only the drain region D1 and the source region S3, respectively, of the neighbor selection transistors are depicted. The selection transistor associated to trench capacitor GK2 comprises a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected to a (not shown) bit line arranged above an isolation layer I via a bit line contact BLK. The drain region D2 is connected to said buried contact 15b on a single side. Above the channel region K2, a word line WL2 is located which comprises a gate stack GS2 and a surrounding gate isolator GI2. The word line WL2 is an active word line for the selection transistor of the trench capacitor GK2.
Word lines WL1 comprising gate stack GS1 and gate isolator GI1 and word line WL3 comprising gate stack GS3 and gate isolator GI3 are running in parallel to the word line WL2, word lines WL1 and WL3 being passive word lines for the selection transistor of the trench capacitor GK2. The word lines WL1, WL3 are adapted for controlling selection transistors which are shifted in the third dimension with respect to said cross-section.
It may be obtained from FIG. 1 that this kind of single-sided connection of the buried contact allows a direct arrangement of the trenches and the neighboring source regions or drain regions of the associated selection transistors next to each other. Thus, the length of a memory cell can amount to only 4 F, and the width can amount to only 2 F, F being the minimum length unit which may be realized in a technological respect (cmp. FIG. 2a, 2b).
FIG. 2A shows a view from above onto a memory cell field having memory cells according FIG. 1 in a first arrangement possibility.
Reference sign DT in FIG. 2A denotes trenches which are arranged in rows having a distance of 3 F and in columns having a distance of 2 F to each other. Neighboring rows are shifted by 2 F with respect to each other. UC in FIG. 2A denotes the area of the unit cell which amounts to 4 F×2 F=8 F2. STI denotes isolation trenches which are arranged in row direction in a distance of 1 F to each other and which isolate neighboring active regions from each other. Also, with a distance of 1 F to each other, bit lines BL are arranged in row direction, whereas said word lines in column direction have a distance of 1 F to each other. In this arrangement example, all trenches DT have a contact region KS of the buried contact to the substrate on the left side and an isolation region IS on the right side (regions 15a,b and 16a,b, respectively, in FIG. 1).
FIG. 2B shows a view from above onto a memory cell field having memory cells according to FIG. 1 in a second arrangement possibility.
In this second arrangement possibility, the rows of the trenches have alternating connection regions or isolation regions of the buried contacts. Thus, in the lowest row of FIG. 2B, the buried contacts have on the left side a contact region KS1 and on the right side a isolation region IS1. On the other hand, in the row laying above, all trenches DT have an isolation region IS2 on the left side and a contact region KS2 on the right side. This arrangement alternates in column direction.
For DRAM memory devices having trench capacitors in sub-100 nm technologies, the resistance of the trench and the buried contact make up a main contribution to the total RC delay and determine the speed of the DRAM. Caused by the relatively low conductivity and the pinch-off which is produced by an overlay displacement of the STI etch, the series resistance in the trench is enhanced dramatically.
This problem was diminished by the introduction of polysilicon highly doped with arsenic, an improvement of the overlay between the active regions and the trench, the introduction of a self-aligned manufacture of a buried contact with single-sided connection, and a thinning of the nitride contact region of the buried contact. Particularly, the upper region of the polysilicon filling highly doped with arsenic in the trench constitutes a big problem for the sub-100 nm technologies, because the doping level cannot be further enhanced and the diameter is influenced by the STI trench formation (STI=Shallow Trench Isolation).